Method for improved process latitude by elongated via integration

ABSTRACT

Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.

FIELD OF THE INVENTION

The present invention pertains to the process of producing intralayerand interlayer structures in Very-Large Scale Integrated (VLSI) andUltra-Large Scale Integrated (ULSI) devices and high performancepackaging. More particularly, the present invention relates tofabricating interconnect dual damascene structures.

BACKGROUND OF THE INVENTION

The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-LargeScale Integrated circuit (ULSI) requires metallic wiring that connectsindividual devices in a semiconductor chip, to one another. One methodof creating this wiring network on such a small scale is the dualdamascene (DD) process schematically shown in FIG. 1. In the standard DDprocess, an interlayer dielectric (ILD), shown as two layers 110, 120 iscoated on the substrate 100, FIG. 1 a. The via level dielectric 110 andthe line level dielectric 120 are shown separately for clarity of theprocess flow description. In general, these two layers can be made ofthe same or different insulating films and in the former case applied asa single monolithic layer.

A hard mask layer 130 is optionally employed to facilitate etchselectivity and to serve as a polish stop in a subsequent fabricationstep. The wiring interconnect network includes two types of features:line features that traverse a distance across the chip, and the viafeatures which connect together lines in different levels. Historically,both layers are made from an inorganic glass such as silicon dioxide(SiO₂) or a fluorinated silica film deposited, for instance, by plasmaenhanced chemical vapor deposition (PECVD).

In the dual damascene process, the position of the lines 150 and thevias 170 are defined lithographically in photoresist layer, 140,depicted in FIGS. 1 b and 1 d, and transferred into the hard mask, 130and ILD layers, 110 and 120, using reactive ion etching processes. Theprocess sequence shown in FIG. 1 is called a Line-first approach becausethe trench 160 which will subsequently house the line feature is etchedfirst, see FIG. 1 c.

After the trench formation, lithography is used to define a via pattern170 in the photoresist layer 140 which is transferred into thedielectric material, 110, to generate a via opening 180. See FIG. 1 d.

The dual damascene trench and via structure 190 is shown in FIG. 1 eafter the photoresist has been stripped. This structure 190 is coatedwith a conducting liner or material or material stack 200 that serves asan adhesion layer between the conductor and the ILD. This recess is thenfilled with a conducting fill material 210 over the surface of thepatterned substrate. The fill is most commonly accomplished byelectroplating of copper although other methods such as chemical vapordeposition (CVD) and other materials such as Al, Ag or Au and alloysthereof can also be used. The fill, 210, and liner, 200 materials arethen chemically-mechanically polished (CMP) to be coplanar with thesurface of the hard mask, 130, and the structure at this stage is shownin FIG. 1 f. A capping material 220 can be deposited over the metal oras a blanket film, as is depicted in FIG. 1 g to passivate the exposedmetal surface and to serve as a diffusion barrier between the metal andany additional ILD layers to be deposited over them. Silicon nitride,silicon carbide, and silicon carbonitride films deposited by PECVD aretypically used as the capping material 220. This process sequence isrepeated for each level of the interconnect on the device. Since twointerconnect features are defined to form a conductor in-lay within aninsulator by a single polish step, this process is designated a dualdamascene process.

In order to improve performance, the semiconductor industry has shrunkthe gate length and as a result the chip size. As a consequence theinterconnect structure that forms the metallic circuitry has alsoshrunk. Traditionally, the via levels are one of the most challenging toprint with a high process latitude. In order to improve themanufacturability of the lithography step, advanced masks thatincorporate phase-shifting, resolution enhancing techniques and opticalproximity correction have been employed. Nevertheless, continuingefforts are underway to develop further improved interconnectfabrication techniques.

SUMMARY OF THE INVENTION

The present invention relates to the fabrication of an interconnectstructure utilizing an advantageous sequence that allows for theelimination of some of the constraints on the via level patterning. Thepresent invention is applicable to any two pattern levels that whenspatially overlaided, their intersection produce the desired viaopening.

The fabrication method of the present invention relates to providing ainterconnect dual damascene structure. The process comprises thefollowing:

a) providing a layer of at least one dielectric on a substrate surface;

b) depositing on the layer of the at least one dielectric, a maskforming layer for providing a via-level mask layer;

c) creating an elongated via pattern in the via-level mask layer;

d) depositing a layer of line-level dielectric;

e) creating a line pattern through the layer of line-level dielectric;

f) transferring the line pattern through the projected intersection ofthe elongated via-level pattern and of the line level pattern togenerate an aligned dual damascene structure;

g) depositing a conductive liner layer and then filling the dualdamascene structure with a conductive fill metal to form a set of metallines;

h) planarizing the metal and liner layers so that the metal is coplanarwith the top of layer of at least one dielectric on the substratesurface.

The present invention also relates to interconnect structures obtainedby the above disclosed process.

A further aspect of the present invention relates to an interconnectdual damascene structure which comprises an aligned dual damascenepattern of a line level pattern and an elongated via-level pattern; aconductive liner layer and conductive fill metal in the aligned dualdamascene pattern forming a set of metal lines; and wherein theconductive liner layer and metal are coplanar with the top layer of thedamascene pattern.

The foregoing and other objects, features and advantages of theinvention as well as presently preferred embodiments thereof and thebest known techniques for fabricating integrated circuit structure inaccordance with the invention will become more apparent from a readingof the following description in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a-1 g are schematic views of the steps in a conventional DualDamascene (DD) Process.

FIGS. 2 a-2 b are schematic views of the steps used to implement a DualDamascene Process with improved process latitude at the via levelaccording to the present invention.

FIGS. 3 a-3 d are schematic views of via narrowing problem occurringwith a conventional Dual Damascene Process.

FIGS. 4 a-4 d are schematic views for addressing via narrowing accordingto the present invention.

BEST AND VARIOUS MODES FOR CARRYING OUT INVENTION

In order to facilitate a further understanding of the present invention,reference will be made to the Figures.

Reference to FIG. 2 a shows coating a substrate 10 with a via-leveldielectric 11 and a via-level mask 12. Typical insulating or dielectricmaterial 11 include silicon dioxide (SiO₂) phosphosilicate glass (PSG),boron doped PSG (BDPSG) or tetraethylorthosilicate (TEOS), and moretypically low-k dielectrics having a dielectric constant of less than3.9 such as SILK (available from Dow Chemical), SiCH (available fromAMAT under the trade designation BLOK), SiCOH (available from Novellusunder the trade designation Coral, from AMAT under the trade designationBlack Diamond and from ASM under the trade designation Auora), SiCHN(available from IBM under the trade designation N Blok), CVDcarbon-doped oxide, porous CVD carbon-doped oxide, porous and non-porousorgano silicates, porous and non-porous organic spin-on polymers.

The via-level mask 12 is typically a hard mask material such as siliconnitride, N Blok, Blok, Coral, Black Diamond, SiCOH, or an organic masksuch as FFO2 from Honeywell. The via-level mask may optionally be amultilayered stack of the hard mask materials. The via-level mask ispatterned using conventional techniques such as reactive ion etching(RIE). The pattern 13 according to the present invention is an elongatedvia pattern. The via pattern is elongated orthogonally relative to thesubsequent to be formed line-level pattern. The pattern 13 is typicallyelongated to at least about 10% of the desired line spacing. The pattern13 is typically elongated to less than ½ the desired line spacing.Preferably pattern 13 is elongated from about 10% to less than ½ thedesired line spacing. See FIG. 2 b. The minimum elongation is typicallydetermined not by the desired line spacing but by the overlay tolerancewith the subsequent pattern is placed.

Next a layer 14 of line-level dielectric is deposited in pattern 13 ontop of patterned mask 12. See FIG. 2 c. The line-level dielectric layer14 is typically any of the dielectrics disclosed above for the via-leveldielectric 11. A mask layer 15 such as a hardmask or hardmask stack iscoated on the line-level dielectric and is patterned with a conventionalline-level pattern 16.

Suitable hardmask materials are tailored by the particular dielectricmaterials used in constructing the structure and can be determined bythose skilled in the art without undue experimentation once aware ofthis disclosure. For example, when employing Silk, the hardmasks cancomprise SiCOH, Blok, SiO₂, NBlok, Si₃N₄, and spin-on silsesquioxanes.For SiCOH based structures, the hardmasks comprises BLOK, RESIST, SiO₂,N BLOK, SiCOH of lower porosity or chemical composition, FSG and TEOS.The mask layer 15 can be etched by reactive ion etching for instance.

The dielectric layer 14 is anisotropically etched to transfer theline-level dielectric to form the troughs 17 as shown in FIG. 2 d.

In addition, where the elongated via patterns is opened in the via-levelmask, the etch progresses to the bottom of the via-level dielectric 10generating the via 18 as shown in FIG. 2 d.

Subsequent conventional metallization and polishing generates the dualdamascene interconnect structure containing the liner 19 and the inlaidconductive material 20 as shown in FIG. 2 e.

Typical barrier layers 19 are tungsten, titanium, tantalum, nitridesthereof and alloys thereof Also, the barrier layer can include two oremore layers (e.g.—W/Wn bilayer). The preferred barrier layer comprisestungsten. The barrier layer 19 is typically deposited by chemical vapordeposition (CVD) or by sputtering such as physical vapor deposition(PVD) or ionized physical vapor deposition (IPVD).

A further example of suitable barrier material is disclosed in U.S. Pat.No. 6,437,440 B1 to Cabral, Jr. et al.

Typical conductive lines 20 are Cu, Al, Ag, Au and alloys thereof, andmore typically Cu and Cu alloys.

The conductive line material can be deposited by these processes knownin the art. When material 20 comprises copper and alloys thereof, thepreferred deposition technique is electroplating such as those disclosedin U.S. Ser. No. 09/348,632 and U.S. Pat. No. 6,331,237 B1 to Andricacoset al.

Next, the dual damascene structure is capped with a electromigration anddiffusion barrier 21 shown in FIG. 2 f as a continuous dielectric cap.Silicon nitride, silicon carbide, and silicon carbonitride filmsdeposited by PECVD are typically used as the capping material 220.

One problem addressed with this integration strategy of the presentinvention is illustrated in FIG. 3. A representative line-level patterncontaining parallel line is shown in FIG. 3 a. A representativevia-level pattern is shown in FIG. 3 b with an aligned line-levelpattern overlaid in the dashed line. The problem addressed in thispatent is illustrated in FIG. 3 c, where the via-level pattern is offsetfrom the line-level pattern illustrated in dashed line. Either vianarrowing represented in FIG. 3 d or line narrowing (not illustrated)will occur. In FIG. 3 d, the via pattern 30 in the resist 34 is offsetfrom the line pattern resulting in the via narrowing 32. This adverselyaffects the via resistance by decreasing the cross-section through whichthe current must flow. Conversely, in the non-illustrated example ofline narrowing, the breakdown voltage will be adversely affected sincetwo adjacent lines will have a narrowed spacing; effectively increasingthe electric field at the location of the vias.

In addition, the integration strategy shown in FIG. 2 may be adoptedthat allows for the via-alignment constraint to be relaxed. In theprocess flow described in FIG. 2, the via reticle (FIG. 4 b) is designedsuch that the vertical intersection of the printed via pattern and theprinted line pattern equates to the desired via pattern. Since the linepatterns on most chips are mostly parallel to one another as shown inFIG. 4 a, a via pattern that is elongated orthogonal (FIG. 4 b) to theline pattern and to length of less than ½ the line width will meet thenew constraint that vertical projected intersection of the two patternsresult in the “perfect” alignment of the via within the width of theline thus negating via narrowing and/or line width spacing as shown inFIG. 4 b. This integration (including the reticle design) allows forvia-to-line misalignment to be accommodated without adversely affectingthe result as is shown in FIG. 4 c. A cross-section view of the B-Bsection in FIG. 4 c is shown in FIG. 4 d where the trough 17 and the via18 are shown with respect to the via-level dielectric 11, via level mask12 with elongated via pattern 13, the line level dielectric 14 andhardmask 15.

The foregoing description of the invention illustrates and describes thepresent invention. Additionally, the disclosure shows and describes onlythe preferred embodiments of the invention but, as mentioned above, itis to be understood that the invention is capable of use in variousother combinations, modifications, and environments and is capable ofchanges or modifications within the scope of the invention concept asexpressed herein, commensurate with the above teachings and/or the skillor knowledge of the relevant art. The embodiments described hereinaboveare further intended to explain best modes known of practicing theinvention and to enable others skilled in the art to utilize theinvention in such, or other, embodiments and with the variousmodifications required by the particular applications or uses of theinvention. Accordingly, the description is not intended to limit theinvention to the form disclosed herein. Also, it is intended that theappended claims be construed to include alternative embodiments.

All publications and patent applications cited in this specification areherein incorporated by reference, and for any and all purposes, as ifeach individual publication or patent application were specifically andindividually indicated to be incorporated by reference.

1. A Very-Large Scale Integrated (VLSI) device or Ultra-Large ScaleIntegrated (ULSI) device that comprises an interconnect structurecomprising an aligned dual damascene pattern of a line level pattern andan elongated via-level pattern; a conductive liner layer and conductivefill metal in the aligned dual damascene pattern forming a set of metallines; and wherein the conductive liner layer and metal are coplanarwith the top layer of the damascene pattern, and wherein said elongatedvia pattern is elongated in the orthogonal direction to said line levelpattern; and wherein said dual damascene structure is self aligned insaid orthogonal direction.
 2. The Very-Large Scale Integrated (VLSI)device or Ultra-Large Scale Integrated (ULSI) device of claim 1, whereinthe interconnect structure further comprises mask-forming layers thatare hardmask materials.
 3. The Very-Large Scale Integrated (VLSI) deviceor Ultra-Large Scale Integrated (ULSI) device of claim 1, wherein theelongated via pattern is elongated by at least 10% of the line-to-linespacing.
 4. The Very-Large Scale Integrated (VLSI) device or Ultra-LargeScale Integrated (ULSI) device of claim 1, wherein the elongated viapattern is elongated by less than ½ the line-to-line spacing.
 5. TheVery-Large Scale Integrated (VLSI) device or Ultra-Large ScaleIntegrated (ULSI) device of claim 1, wherein the elongated via patternis elongated from about 10% to less than ½ the line-to-line spacing. 6.The Very-Large Scale Integrated (VLSI) device or Ultra-Large ScaleIntegrated (ULSI) device of claim 1, wherein the conductive fillmaterial comprises Cu or Ag alloy.
 7. The Very-Large Scale Integrated(VLSI) device or Ultra-Large Scale Integrated (ULSI) device of claim 1,wherein the interconnect structure further comprises a capping layer.